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regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is n ecessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein.
hitachi single-chip microcomputer h8s series technical q&a h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124 application note ade-502-059 rev. 1.0 3/5/03 hitachi, ltd ou g i t
notice when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications.
preface the h8s/2000 series is a new series of hitachi-original high-performance 16-bit microcomputers designed to offer higher performance and lower power consumption than existing h8 series models, which are widely used in equipment control, and provide much greater ease of use. these microcomputers include a cpu, ram, rom, dma controller, data transfer controller, bus controller, timers, sci, a/d converter, and other on-chip supporting modules, making them suitable for use in a wide range of applications from small to large-scale systems. another major feature of the h8s/2000 series is upward-compatibility at the cpu object code level with the h8/300h, h8/300, and h8/300l series within the h8 series, allowing the use of existing software resources. this microcomputer technical q&a application note covers the h8s/2655 series, h8s/2350 series, h8s/2355 series, h8s/2357, h8s/2345 series, h8s/2245 series, h8s/2148 series, h8s/2144 series, h8s/2138 series, h8s/2134 series, h8s/2128 series, and h8s/2124 series.

using this application note this application note is a compilation of responses to queries from hitachi microcomputer users, presented in question and answer format. it should be used in conjunction with the relevant users manuals. it may also be helpful to read through this manual before beginning design work on products using h8s series microcomputers, to gain more in-depth knowledge of the microcomputer products, and as a reminder of items that may present difficulties in the design stage.

i contents cpu cpu subject: use of general registers .............................................................................................. .. 1 subject: difference between v flag and c flag in ccr ............................................................. 2 subject: relationship between data size and change of v flag ................................................. 4 subject: area usable as rom in vector table............................................................................ 5 subject: h8s/2000 cpu normal mode........................................................................................ 6 subject: mac register .......................................................................................................... ....... 7 subject: exr register.......................................................................................................... ........ 8 instruction subject: subx instruction ...................................................................................................... ..... 9 subject: brn instruction....................................................................................................... ....... 10 subject: difference between bra instruction and jmp instruction............................................ 11 subject: bra and brn instructions ............................................................................................ 12 subject: support of daa (das) instruction corresponding to inc (dec) instruction ............. 13 subject: odd address value when stc instruction is executed ................................................. 14 subject: stack precautions..................................................................................................... ....... 15 subject: stack pointer ......................................................................................................... .......... 16 subject: tas instruction ....................................................................................................... ....... 17 subject: bld and bist instructions............................................................................................ 1 8 subject: bor and biand instructions........................................................................................ 20 mcu operating modes subject: mode pins ............................................................................................................. .......... 22 subject: use of rame bit ....................................................................................................... .... 23 exception handling subject: reset................................................................................................................. ............... 24 interrupts subject: handling of interrupt requests when irq interrupts are disabled................................ 26 subject: handling of interrupt requests when interrupts are masked ......................................... 27 subject: use of irq status register............................................................................................ .28 subject: interrupt disable timing (1).......................................................................................... .29 subject: interrupt disable timing (2).......................................................................................... .30 subject: interrupt immediately after reset ................................................................................... 31 subject: simultaneous irq interrupts of the same priority......................................................... 32
ii subject: use of different interrupt modes ................................................................................... 33 subject: insufficient number of external interrupts .................................................................... 35 bus controller subject: cs state in on-chip ram and internal i/o access ...................................................... 36 subject: f clock state when bus is released............................................................................... 37 subject: wait (1) ........................................................................................................................ 38 subject: wait (2) ........................................................................................................................ 39 subject: program wait switchover timing.................................................................................. 41 subject: breq acceptance in power-down modes.................................................................... 43 subject: external connection of ram to 8-bit-access space .................................................... 44 subject: bus controller settings for area 7 ................................................................................. 45 subject: external bus states during cpu operation .................................................................... 47 subject: internal i/o register access when bus is released ....................................................... 48 subject: cs signals after power-on reset ................................................................................... 49 subject: bus release wait time after breq input ..................................................................... 50 subject: external bus right release and refresh control........................................................... 51 subject: 2-cas dram interface ................................................................................................. 5 2 power-down state subject: medium-speed mode ..................................................................................................... 54 subject: oscillation settling wait time after software standby mode ....................................... 55 subject: on-chip supporting modules in software standby mode ............................................ 56 subject: mode pins (md2 to md0) in hardware standby mode ................................................ 57 subject: hardware standby mode at power-on........................................................................... 58 subject: module stop mode ...................................................................................................... ... 59 subject: timer output in module stop mode .............................................................................. 60 electrical characteristics subject: current dissipation value ............................................................................................. .61 subject: rd signal timing........................................................................................................... 62 pins subject: handling of unused pins............................................................................................... .64 subject: res pin, stby pin, and nmi pin input circuits .......................................................... 65 subject: address pin states in on-chip memory access ............................................................ 66 subject: built-in mos pull-ups in reset..................................................................................... 68 subject: wdtovf pin ................................................................................................................. 69
iii on-chip i/o dmac subject: number of states between transfers.............................................................................. 71 subject: maximum transfer rate................................................................................................. 72 subject: difference between dmac and dtc ............................................................................ 73 subject: alternate 8-bit/16-bit space accesses........................................................................... 74 subject: tend signal output conditions when using write buffer function........................... 76 subject: interrupt acceptance after end of transfer ................................................................... 78 subject: handling of transfer request before start of transfer.................................................. 79 subject: activation request signal detection.............................................................................. 80 subject: short address mode and full address mode ................................................................ 82 subject: bus right in standby state ............................................................................................ .83 subject: handling of transfer end interrupt ................................................................................ 84 subject: dreq signal input......................................................................................................... 86 dtc subject: nature of dtc ......................................................................................................... ....... 87 subject: maximum number of channels ..................................................................................... 88 subject: setting register information .......................................................................................... 89 subject: order of setting register information............................................................................ 90 subject: use of dtc interrupt select bit (disel) ...................................................................... 91 tpu (16-bit timers) subject: non-timer use of port ................................................................................................. .. 92 subject: cascaded connection................................................................................................... ... 93 subject: dual use of pwm mode 1 and input capture ............................................................... 94 subject: setting pwm mode 2 cycle........................................................................................... 95 subject: synchronous operation of two sets .............................................................................. 96 subject: two-phase pwm output................................................................................................ 97 wdt subject: interval timer with arbitrary time interval .................................................................. 99 sci subject: sci initialization.................................................................................................... ......... 100 subject: difference between tdre flag and tend flag........................................................... 101 subject: initial state of txd pin.............................................................................................. ..... 102 subject: maximum external clock input value (asynchronous mode)...................................... 103 subject: transmit/receive operation in synchronous mode ...................................................... 104 subject: sci transmission using dtc........................................................................................ 105 subject: permissible bit rate error in asynchronous mode........................................................ 106 subject: operation of rdrf flag ................................................................................................ 109
iv subject: rdrf flag set timing .................................................................................................. . 110 subject: interrupt source flag clearing ....................................................................................... 1 13 subject: continuous transmission/reception in synchronous mode using external clock...... 114 subject: use of rdr and tdr when sci is not used................................................................ 115 subject: sci clock pin input/output setting ............................................................................... 116 subject: serial internal i/o pin states ........................................................................................ .. 117 subject: setting asynchronous mode .......................................................................................... 118 subject: data transfer to tdr .................................................................................................. ... 121 subject: tdre flag set timing .................................................................................................. . 123 subject: phases of system clock and sck .................................................................................. 127 a/d converter subject: idea behind external c and r ........................................................................................ 12 8 subject: a/d conversion in simultaneous sampling operation.................................................. 130 subject: a/d conversion time in simultaneous sampling operation ........................................ 132 i/o ports subject: i/o port manipulation................................................................................................. .... 134 subject: reserved bits......................................................................................................... ......... 135 subject: disabling f output.......................................................................................................... 136 subject: port 3 open-drain output .............................................................................................. 137 subject: multiplexing as irq3 and lwr ..................................................................................... 138 clock pulse generator subject: crystal resonator capacitance value ............................................................................ 139
1 microcomputer technical q&a q&a no.: qah8s-001 category: cpu subject: use of general registers question is it possible to use a mix of 8-bit, 16-bit, and 32-bit general registers? answer yes. individual registers can be used in any way desired, as shown below. e0 e2 e4 e5 e6 r0h r2h r6h r0l r2l r4 r5 r6l er1 er3 er7 (sp) example: however, note that er7 is used implicitly as the sp. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 2 q&a no.: qah8s-002 category: cpu subject: difference between v flag and c flag in ccr question the v flag and c flag in ccr are both set if overflow occurs during an operation. what is the difference between these flags? answer the v flag in ccr is used to identify whether overflow occurs in a signed operation. to take the example of a byte-size operation, this flag is set to 1 if the operation result is smaller than the negative minimum value (h'80) larger than the positive maximum value (h'7f). v flag h'80 h'7f h'00 overflow overflow the c flag, on the other hand, is used to identify whether overflow occurs in an unsigned operation. to take the example of a byte-size operation, this flag is set to 1 if the operation result is larger than the maximum value (h'ff) or smaller than the minimum value (h'00). c flag h'00 h'ff overflow overflow
microcomputer technical q&a 3 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 4 q&a no.: qah8s-003 category: cpu subject: relationship between data size and change of v flag question do changes of the v flag in the condition code register (ccr) depend on the data size? answer the v flag changes on detection of overflow in the result of a signed arithmetic operation. the change operation is the same regardless of the data size, but the times when the flag changes differ as shown below. byte size: in the case of a value larger than h'7f or smaller than h'80 word size: in the case of a value larger than h'7fff or smaller than h'8000 longword size: in the case of a value larger than h'7fffffff or smaller than h'80000000 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 5 q&a no.: qah8s-004 category: cpu subject: area usable as rom in vector table questions 1. can a free area in the vector table (reserved, or reserved for system use) be used as rom? 2. can a free area in the internal i/o register area by used as rom? answers 1. vector numbers 0 to 6 and 12 to 15 reserved for system use in the vector table cannot be used. reserved addresses can be used as rom. vector addresses for unused interrupts in the vector table can also be used as rom. 2. free i/o register areas cannot be used. additional explanation areas reserved for system use can be used by development tools. addresses of areas reserved for system use, and reserved area addresses, should be checked manually. in a memory-indirect-addressing branch address area, addresses other than those reserved for system use and the used vector table addresses can be used. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 6 q&a no.: qah8s-005 category: cpu subject: h8s/2000 cpu normal mode question are any precautions required when making a transition from h8/300 series to h8s/2000 series normal mode? answer in h8s normal mode, address registers are recognized as being 32 bits long. therefore, the following changes are necessary when using an h8/300 assembler program. register indirect example: mov.b @r0,r1l ? mov.b @er0,r1l an error is not flagged during assembly. access is possible regardless of the contents of the extended register (e0). adds/subs instruction example: adds.w r0 ? adds.l er0 or inc.w r0 sp (stack pointer) example: mov.w #16,sp ? mov.l #:32,sp or mov.w #:16,r7 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 7 q&a no.: qah8s-006 category: cpu subject: mac register question why is the mac register 42 bits long? answer the mac register is used to store the value obtained by adding together the result of a multiplication and the value in the register itself. the multiplication result is 32 bits (from a 16-bit 16-bit operation), and if the mac register value is added as 32 bits, overflow may occur. to prevent overflow, therefore, the 32 bits are increased by 10 bits, giving 42 bits (so that overflow will not occur even if 2 10 = 1024 multiply-and-accumulate operations are performed). applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 8 q&a no.: qah8s-007 category: cpu subject: exr register question why has the exr registers been added? answer there are two reasons: providing 8 interrupt mask levels using i2 to i0 enables multiple interrupt handling to be speeded up. trace functions are implemented using the t bit. when the t bit is set to 1, trace exception handling is started each time an instruction is executed. for details, see the hardware manual. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 9 q&a no.: qah8s-008 category: instruction subject: subx instruction question why is the z flag value unchanged when the result of a subx (subtraction with carry) instruction operation is 0? answer this is because the subx instruction operation result is anded with the z flag value before execution of the instruction. the logical equation is shown below. z = z' rm rm-1 ... r0 when the execution result is 0, rm rm-1 ... r0 (abbreviated to rn below) is 1. as the z flag value for this instruction is the and of rn and z', when the execution result is 0, the z flag value is held. notes: m = 31 (longword size), 15 (word-size), or 8 (byte-size) ri = bit i of result z' = z flag value before instruction execution applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 10 q&a no.: qah8s-009 category: instruction subject: brn instruction question what kind of instruction is brn (bf)? answer the brn instruction is useful as a replacement for a conditional branch instruction during debugging. the operation of the brn instruction is similar to that of the nop instruction, but the instruction size and instruction execution time are different, as shown below. instruction instruction size (bytes) instruction execution time (states) brn d:8 2 2 * d:16 4 3 * nop 2 1 * note: * when the instruction is fetched from on-chip rom note: like brn, the bra (bt) instruction is useful for debugging, etc. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 11 q&a no.: qah8s-010 category: instruction subject: difference between bra instruction and jmp instruction question what is the difference between the bra (bt) instruction and the jmp instruction? answer with the bra instruction, a branch is made on the basis of the address at which the bra instruction is located, whereas with the jmp instruction, the branch address is specified indirectly. the differences between these two instructions are summarized below. with the bra instruction, the branching range is limited to +127 bytes to C128 bytes for d:8, and +32767 bytes to C32768 bytes for d:16. with the bra instruction, program relocation is possible if the relative value with respect to the branch destination is changed. the instruction length and number of execution states are different. for these two instructions. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 12 q&a no.: qah8s-011 category: instruction subject: bra and brn instructions questions 1. what does it mean when the bra (bt) instruction condition is true? 2. what does it mean when the brn (bf) instruction condition is false? answers 1. since the bra instruction always branches (always), this means that the branch condition is always true. 2. since the brn instruction never branches (never), this means that the branch condition is always false. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 13 q&a no.: qah8s-012 category: instruction subject: support of daa (das) instruction corresponding to inc (dec) instruction questions 1. the daa instruction is used for an add instruction (add instruction). what operation is performed if a daa instruction is executed after an inc instruction? 2. the das instruction is used for a subtract instruction (sub instruction). what operation is performed if a das instruction is executed after a dec instruction? answers 1. use of the daa instruction after execution of an inc instruction is not supported. this is because the operation result is indicated by the c and h flags after an inc instruction is executed. to decrement decimal data, add C1 with an add instruction (add.b #C1, rd), then execute a daa instruction. 2. use of the das instruction after execution of a dec instruction is not supported. this is because the operation result is indicated by the c and h flags after a dec instruction is executed. to decrement decimal data, add 1 with an add instruction (add.b #1, rd), then invert the c and h flags (xorc #a0, ccr) and execute a das instruction. note: however, the actual operation is determined by the flag statuses. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 14 q&a no.: qah8s-013 category: instruction subject: odd address value when stc instruction is executed question the manual states that when the stc instruction is executed, the ccr value is stored in the (register-indirect) even address. what is the value in the odd address? answer the value is undefined. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 15 q&a no.: qah8s-014 category: instruction subject: stack precautions question are any precautions required concerning the stacking method? answer the cpu always uses word-size or longword-size access to the stack area. setting the sp (stack pointer) to an odd value may result in misoperation. the push, pop, stm, and ldm instructions should be used for stacking. the initial value of the stack pointer is undefined, and must be set by the user. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 16 q&a no.: qah8s-015 category: instruction subject: stack pointer question how should the stack pointer (sp: er7) be initialized? answer to reserve the stack after the end of on-chip ram, for example, set the initial value of the stack pointer as 1 greater than the last address of on-chip ram. h'fffbff h'fffc00 first stack sp initial value used as stack not used as stack on-chip ram initial set value of stack pointer (addresses are for h8s/2655 series) applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 17 q&a no.: qah8s-016 category: instruction subject: tas instruction question what is the meaning of the test and set instruction (tas)? answer the tas instruction test memory contents, then sets the most significant bit (bit 7) to 1. this is a read-modify-write instruction, and the bus cannot be released during these operations. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 18 q&a no.: qah8s-017 category: instruction subject: bld and bist instructions question how are bit-manipulation instructions such as bld and bist used? answer these instructions can be used to invert any bit data in memory, and store the value in a bit of another memory address, as shown in the flowchart below. start end bit n of in = 0? bit n of out ? 1 bit n of out ? 0 no yes using bld and bist not using bld and bist bld #n,@in bist #m,@out btst #n,@in bne l1 bset #n,@out bra l2 l1: bclr #n,@out l2: 8 bytes/7 states 16 bytes/11 states
microcomputer technical q&a 19 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 20 q&a no.: qah8s-018 category: instruction subject: bor and biand instructions question how are bit-manipulation instructions such as bor and biand used? answer these instructions are used to branch after looking at a number of flags. an example of their use is shown below. start next l1 bit n of in1 = 0? bit n of in2 = 0? no no yes yes example: to branch to l1 when in1 flag = 1 and in2 flag = 0 using bor/biand not using bor/biand bld #n,@in1 biand #m,@in2 bcs l1 btst #n,@in1 bnq next bset #m,@in2 bne next bra l1 next: 10 bytes/8 states 14 bytes/10 states
microcomputer technical q&a 21 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 22 q&a no.: qah8s-019 category: mcu operating modes subject: mode pins questions 1. is it possible to change the mcu operating mode during normal operation? 2. is there any way of fixing the mcu operating mode (preventing a change of mcu operating mode due to noise, etc.)? answers 1. the mcu operating mode cannot be changed during normal operation, as this would cause misoperation. 2. read the memory control register (mdcr). when mdcr is read, the input levels of the mode pins (md2 to md0) *1 are latched in the corresponding bits. as these latches are cleared by a power-on reset but not by a manual reset *2 , a change of mcu operating mode during operation can be prevented in this way. notes: 1. in the h8s/2100 series, the mode pins are md1 and md0. 2. there is no manual reset in the h8s/2100 series. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 23 q&a no.: qah8s-020 category: mcu operating modes subject: use of rame bit question how is the rame bit used? answer the rame bit is used for on-chip ram protection, etc. since cpu operation is halted asynchronously in hardware standby mode, there is a risk of losing the on-chip ram contents. on-chip ram contents can be protected by disabling the on-chip ram with the rame bit before processing is executed. also, the same addresses can be overlapped internally and externally by disabling ram. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 24 q&a no.: qah8s-021 category: exception handling subject: reset question a reset time of at least 20 ms is specified. does this also apply when an external clock is used? answer no, this specification does not apply in the case of an external clock. when an external clock is used, the reset time should be at least 500 s. a reset of at least the length of the external clock output settling delay time (t dext = 500 s) is necessary to allow the clock output to stabilize (see figure below). extal v cc res t dext f oscillation settling timing
microcomputer technical q&a 25 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 26 q&a no.: qah8s-022 category: interrupts subject: handling of interrupt requests when irq interrupts are disabled question is an irqn interrupt request held pending if generated while the irqne bit is cleared to 0 in the irq enable register (ier)? answer yes. when the signal specified in the irq sense control register (iscr) is input to the irqn pin, irqnf (the irqn flag) is set to 1 in the irq status register (isr). this does not depend on the status of the irqne bit. if the irqne bit is set to 1 while irqnf is set to 1, an interrupt is requested. irqnf can be cleared to 0 by software. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 27 q&a no.: qah8s-023 category: interrupts subject: handling of interrupt requests when interrupts are masked question is an irqnf interrupt request held pending if generated when interrupts are masked by the i and ui bits, or bits i2 to i0, in the condition code register (ccr)? answer yes. irqnf is independent of the status of the i and ui bits. if interrupt masking is released while the irqnf and irqne bits are set to 1, the interrupt will be accepted. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 28 q&a no.: qah8s-024 category: interrupts subject: use of irq status register question the irq status register (isr) can be cleared to 0 by the user. when is this register used? answer the irq status register is cleared to 0 automatically. therefore, the user consciously clears this register in the following cases: in level sensing if there is a risk of generation of an unwanted interrupt before interrupts are enabled (e.g. during initialization or when pin connections are changed), total clearing can be performed directly before enabling interrupts when irq status register bits are used as flags, without enabling interrupts when multiplication interrupts are generated, to execute only high-priority processing, and not low-priority processing applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 29 q&a no.: qah8s-025 category: interrupts subject: interrupt disable timing (1) question when a supporting module interrupt enable bit is cleared to 0, is the interrupt disabled immediately? answer the interrupt is disabled after execution of the instruction that clears the interrupt enable bit to 0. however, if an interrupt request is generated during execution of the 0-clearing instruction, the interrupt request may be accepted after execution of that instruction. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 30 q&a no.: qah8s-026 category: interrupts subject: interrupt disable timing (2) question when an interrupt enable bit is cleared to 0 in the irq enable register (ier), is the interrupt disabled immediately? answer the interrupt is disabled after execution of the instruction that clears the interrupt enable bit to 0. if an interrupt request is generated during execution of the 0-clearing instruction, since the request signal is cleared in the same way as the enable bit, the interrupt request will not be accepted after execution of the instruction. however, since the irqn flag is held, the interrupt request will be accepted if the corresponding interrupt enable bit is then set to 1. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 31 q&a no.: qah8s-027 category: interrupts subject: interrupt immediately after reset question is an interrupt ever generated immediately after a reset? answer no, never. immediately after a reset, all interrupts, including nmi, are disabled. however, nmi is accepted when the first instruction of the program is executed. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 32 q&a no.: qah8s-028 category: interrupts subject: simultaneous irq interrupts of the same priority questions 1. with external interrupts, if interrupts within the group with the same priority ( irq4 to irq7 ) are generated simultaneously (e.g. irq4 and irq7 ), which has priority? 2. what will happen if an irq4 interrupt is generated in the irq7 interrupt handling routine? (is irq4 held pending, or is irq4 handling given priority?) answers 1. the priority order within the irq4 to irq7 interrupt group is: irq4 > irq5 > irq6 > irq7 . 2. the irq7 interrupt is accepted first. if interrupts are enabled in the irq7 handling routine immediately after the irq7 interrupt is accepted, interrupts irq4 to irq7 can then be accepted. if interrupts are not enabled in the irq7 handling routine, these interrupts can be accepted after returning from the irq7 handling routine. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 33 q&a no.: qah8s-029 category: interrupts subject: use of different interrupt modes question there are four interrupt control modes. how are these different modes used? answer modes 0 and 1 are compatible with the h8/300 series and/or h8/300h series. guidelines for mode selection are given below. mode 0 controlled by the i bit; useful when multiple interrupts are not used. if multiple interrupts are not used, the size of the stack, etc., can be limited. compatible with the h8/300 series and h8/300h series. mode 1 controlled by the i and ui bits. icr can be handled easily as longword data, enabling icr settings to be made at the start of an interrupt routine. exr is not used, enabling the stack size to be limited. compatible with the h8/300h series. mode 2 enables 8-level multiple interruption to be controlled at high speed. note: interrupt control modes differ from product to product; see the relevant hardware manual for details.
microcomputer technical q&a 34 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 35 q&a no.: qah8s-030 category: interrupts subject: insufficient number of external interrupts question can any substitution method be used if more external interrupts are needed? answer tpu input capture can be used as a substitute. an unused tpu timer general register (tgr) is set to input capture. when the designated edge is input at the tioc input, the tgr flag is set and an input capture interrupt is generated. this can be used in the same way as an edge-input irq. 16-bit free-running timer (frt) input capture input can also be used in the same way. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 36 q&a no.: qah8s-031 category: bus controller subject: cs state in on-chip ram and internal i/o access question is the chip select signal ( cs7 ) output when on-chip memory or an internal i/o register (area 7) is accessed in advanced mode? answer no, the chip select signal ( cs7 ) is not output in internal i/o register access, and a chip select signal is not output in on-chip memory access. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 37 q&a no.: qah8s-032 category: bus controller subject: f clock state when bus is released question is the f clock output when the bus is released? answer if the corresponding port data direction register (ddr) bit is set to 1 and the pstop bit in the system control register (syscr) is cleared to 0, the f clock is output when the bus is released. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 38 q&a no.: qah8s-033 category: bus controller subject: wait (1) question when programmable waits are inserted and the pin wait function is also used, by what point should the wait pin level be settled? answer the wait pin level should be settled by the fall of f in the last t2 or tw state. program waits pin waits f wait t1 t2 tw tw tw tw tw tw t3 wait state insertion timing applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 39 q&a no.: qah8s-034 category: bus controller subject: wait (2) question the description of the pin wait function states that program waits are inserted first. are program waits inserted irrespective of the wait control register (wcr) setting? answer as stated in the manual, with pin waits, program waits are inserted in accordance with the wcr setting, followed by pin wait insertion with reference to the wait pin. a flowchart of pin wait insertion is shown below. program waits 1 to 3 0 program wait insertion wait pin high low pin wait insertion pin wait insertion end of pin wait insertion pin wait insertion flowchart
microcomputer technical q&a 40 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 41 q&a no.: qah8s-035 category: bus controller subject: program wait switchover timing question after a power-on reset, 3 program wait states are inserted in an external access cycle, making a 6- state access. when external 3-state access is set, what is the switchover timing? answer the switchover is made immediately after the wait control register (wcrh) is set. to set external 3-state access after a power-on reset, clear the wn0 and wn1 bits in wcr to 0. an example of the switchover timing when waits are disabled by clearing all wcr bits to 0 with a mov instruction is shown below. example: mov.w r1,@h'fed2:16 wcrh (address h'fed2), wcrl (address h'fed3) (assuming 0 is stored in r1) 3 states + 3 waits 3 states + 3 waits 2 states 3 states r:w 2nd r:w next w:w ea mov.w r1,@fed2:16 address rd hwr , lwr
microcomputer technical q&a 42 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 43 q&a no.: qah8s-036 category: bus controller subject: breq acceptance in power-down modes questions 1. is breq accepted in sleep mode? 2. is breq accepted in hardware standby mode or software standby mode? answers 1. yes. (however, in the h8s/2245 series, h8s/2345 series, and h8s/2355 series, breq is not accepted in sleep mode when all modules are stopped.) 2. no, breq is not accepted in hardware standby mode or software standby mode. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 44 q&a no.: qah8s-037 category: bus controller subject: external connection of ram to 8-bit-access space question when ram is connected externally to 8-bit-access space, is the hwr signal or the lwr signal used for access? answer the hwr signal is used. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 45 q&a no.: qah8s-038 category: bus controller subject: bus controller settings for area 7 question area 7 includes a mix of on-chip ram and internal i/o registers. for which areas are the bus width and number of access states set in the bus controller valid? answer in area 7, the bus width and number of access states set in the bus controller are valid for areas other than on-chip ram and internal i/o registers*. the bus width and number of access states for on-chip ram and on-chip supporting modules are fixed as shown in the table below. note: * depends on the product; see the relevant hardware manual for details. cpu bus interface (example of h8s/2655) on-chip modules on-chip memory on-chip supporting modules bus width access bus width access a/d, tpu, 8-bit timers, wdt 16 bits 2 states 16 bits 1 state others 8 bits when the rame bit is cleared to 0 in the system control register (syscr), on-chip ram is disabled, and the area 7 settings are followed. in this case, the cs7 signal goes low for the area 7 ram area.
microcomputer technical q&a 46 applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 47 q&a no.: qah8s-039 category: bus controller subject: external bus states during cpu operation questions 1. what is the state of the external buses during cpu internal processing? 2. what is the state of the external buses after dreq acceptance? 3. what is the state of the external buses after breq acceptance? answer the states in cases 1 to 3 are summarized in the table below. bus states during cpu operation no. bus state address bus data bus 1 during cpu internal processing held high impedance 2 after dreq acceptance dma address dma data 3 after breq acceptance high impedance high impedance applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 48 q&a no.: qah8s-040 category: bus controller subject: internal i/o register access when bus is released question when the h8s/2000 cpu releases the bus to an external device, can the external device (bus master) access h8s series internal registers? answer no, internal i/o registers cannot be accessed by an external device. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 49 q&a no.: qah8s-041 category: bus controller subject: cs signals after power-on reset question what is the state of the cs signals after a power-on reset? answer after a power-on resets, all the cs signals except cs0 are in the input state (in modes 1, 4, and 5). in expanded modes with on-chip rom disabled, vectors and starts of programs should be located in area 0. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 50 q&a no.: qah8s-042 category: bus controller subject: bus release wait time after breq input question in what circumstances is there a long wait time from breq input to back output? answer a breq request is held pending in the following cases: in dmac data transfer in burst mode or block transfer mode in dtc data transfer when a wait is inserted in an external address access applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 51 q&a no.: qah8s-043 category: bus controller subject: external bus right release and refresh control question are refresh requests held pending while the bus is released? answer if a refresh request is generated while the external bus right is released, refresh control is deferred until the external bus master cancels the bus request. only one refresh request is held. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 52 q&a no.: qah8s-044 category: bus controller subject: 2-cas dram interface question please explain the use of the lcass bit with the 2-cas dram interface. answer the lcass bit in bus control register l (bcrl) selects whether the lwr pin or the lcas pin is used for the lcas signal on the 2-cas dram interface. lcass description 0 the lcas pin is used for the 2-cas dram interface lcas signal. more pins are needed for bus control. ( breqo output and wait input cannot be used.) ras down mode can be used, and dram fast page mode can be used effectively. cbr refreshing can be performed in parallel with ordinary space access, limiting the drop in performance due to refreshing. an idle cycle is not necessary in cbr refreshing after dram access. compatible with h8s/2350 series 1 the lwr pin is used for the 2-cas dram interface lcas signal. (initial value) fewer pins are needed for bus control. ( breqo output and wait input can be used.) ras down mode cannot be used. another ordinary space access cannot be performed during the cbr refresh period. an idle cycle is inserted in cbr refreshing after dram access. not compatible with h8s/2350 series clearing the lcass bit to 0 and using the lcas pin for the lcas signal enables dram to be accessed efficiently.
microcomputer technical q&a 53 applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 54 q&a no.: qah8s-045 category: power-down state subject: medium-speed mode question why is it that, in medium-speed mode, a divided clock is supplied to the bus masters (cpu, dtc, dmac), while the original system clock is supplied to the other on-chip supporting modules? answer the internal clock supplied to the on-chip supporting modules is always fixed. therefore, if medium-speed mode is set during sci transmission/reception, for example, sci operation will continue normally even though the bus master clock is changed. medium-speed mode can thus be set at any time without regard to the operation of the on-chip supporting modules. also, non-operating modules can be stopped individually by means of the module stop function. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 55 q&a no.: qah8s-046 category: power-down state subject: oscillation settling wait time after software standby mode question what are the pin states during the oscillation settling wait period after exiting software standby mode? answer the pin states during the oscillation settling wait period in this case are the same as for software standby mode. for details, see the appendix port states in each processing state in the relevant hardware manual. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 56 q&a no.: qah8s-047 category: power-down state subject: on-chip supporting modules in software standby mode question what is the state of the on-chip supporting modules in software standby mode? answer in the h8s series, on-chip supporting module register contents are generally held in software standby mode, and the contents of these registers do not have to be set again when software standby mode is exited. however, some on-chip supporting modules are reset in software standby mode. see the relevant hardware manual for details. example: in the h8s/2655 series, the sci is reset but the states of the other on-chip supporting modules are held. (see table 21.1, operating states, in section 21, power-down state, in the hardware manual.) applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 57 q&a no.: qah8s-048 category: power-down state subject: mode pins (md2 to md0) in hardware standby mode question how does the microcomputer operate if the state of the mode pins (md2 to md0) is changed in hardware standby mode? answer normal hardware standby mode operation will not be performed. in hardware standby mode, as in normal operation, the mode pins (md2 to md0) must not be changed. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 58 q&a no.: qah8s-049 category: power-down state subject: hardware standby mode at power-on question how can hardware standby mode be entered at power-on? answer drive the stby pin low at power-on. note: the mode pins (md2 to md0) must be set to the prescribed input state at this time. (in the h8s/2655 series, at least one of pins md2 to md0 should be driven high, and one of modes 1 to 7 must be selected as the mcu operating mode.) applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 59 q&a no.: qah8s-050 category: power-down state subject: module stop mode question when a write is performed on an 8-bit timer register, the value is not written. why is this? answer immediately after a reset, an h8s series chip enters module stop mode to hold down current dissipation, and the internal i/o registers of the relevant modules cannot be read or written to. module stop mode should be cleared in advance for on-chip supporting modules that are to be used. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 60 q&a no.: qah8s-051 category: power-down state subject: timer output in module stop mode question if module stop mode is set during output compare match output (tioc output) by the tpu, what happens to this output? answer in module stop mode, the tpu stops, and the register contents and tioc output state are held. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 61 q&a no.: qah8s-052 category: electrical characteristics subject: current dissipation value question in the current dissipation entry in the h8s/2245 series electrical characteristics section, there is an item for which three modessleep, all-module-stop, and medium-speed mode ( f / 32)are combined into one. what is this? answer this indicates a state combining all software-controllable power-down states. when these three modes are combined, the current dissipation can be minimized. applicable products applicability series applicability series applicability series entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 62 q&a no.: qah8s-053 category: electrical characteristics subject: rd signal timing question with successive read cycles, does the rd signal go high momentarily when the bus cycle changes, or does it remain low? answer the rd signal goes high momentarily. the rd signal rise delay time t rsd2 and fall delay time t rsd1 are virtually the same (t rsd1 ? t rsd2 ). therefore, the high-level width of the rd signal is as follows: since t rsd1 ? t rsd2 , rd signal high-level width = (t cyc /2) + t rsd1 C t rsd2 ? (t cyc /2) t1 t2 t3 f a23 to a0 t ad t rsd2 hi g h-level width t as t rsd1 t rsd2 rd rd signal timing
microcomputer technical q&a 63 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 64 q&a no.: qah8s-054 category: pins subject: handling of unused pins question how should unused pins be handled? answer for i/o ports and input ports, clear the ddr (data direction register) bits to 0 to set the input state, and pull each pin up or down individually with a resistance of approximately 10 k w . applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 65 q&a no.: qah8s-055 category: pins subject: res pin, stby pin, and nmi pin input circuits question what kind of circuits are the res pin, stby pin, and nmi pin input circuits? answer the res pin, stby pin, and nmi pin are schmitt-trigger inputs. the signals are transferred internally via a noise canceler. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 66 q&a no.: qah8s-056 category: pins subject: address pin states in on-chip memory access question when on-chip rom or on-chip ram is accessed, is the on-chip rom or on-chip ram address output off-chip? answer when on-chip rom, on-chip ram, or an internal i/o register is accessed, the address bus retains its previous address value, and the on-chip rom or on-chip ram address value is not output off- chip (see figure below). this is effective in reducing current dissipation and noise. internal address external address external memory on-chip rom on-chip ram internal i/o register f external memory address held address bus in on-chip rom, on-chip ram, and internal i/o register access
microcomputer technical q&a 67 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 68 q&a no.: qah8s-057 category: pins subject: built-in mos pull-ups in reset question can built-in mos pull-ups be turned on in the reset state? answer in a manual reset, i/o port states are held, and therefore built-in mos pull-ups can be turned on. in a power-on reset, i/o ports are initialized, and therefore built-in mos pull-up settings are cleared. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 69 q&a no.: qah8s-058 category: pins subject: wdtovf pin questions 1. what is the state of the wdtovf pin in hardware standby mode? 2. the wdtovf pin is high during the hardware standby period. please give an example of a circuit that drives this signal low. 3. what is the wdtovf pin output specification? answers 1. in hardware standby mode, the wdtovf pin is high. 2. an example of a circuit that drives the wdtovf signal low during the hardware standby period is shown below. hardware standby input low output h8s series chip stby wdtovf sample wdtovf signal low-level output circuit 3. the wdtovf pin is a cmos output pin.
microcomputer technical q&a 70 applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 71 q&a no.: qah8s-201 category: dmac subject: number of states between transfers question a minimum of two states are necessary between the first dmac transfer and the next. why is this? answer when the dmac is activated, the bus request signal is sent to the bus controller at the rise of the first clock, and enabling is accepted at the fall. at the rise of the next clock, a read/write request is sent to the bus controller. this operation requires two cycles = two states for the bus cycle. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 72 q&a no.: qah8s-202 category: dmac subject: maximum transfer rate question what is the maximum transfer rate for single address transfer? answer two states are required for the dmac activation wait, and two states for a two-word data transfer. thus, at 20 mhz operation, the maximum transfer rate is 16 bits / (2t cyc + 2t cyc ) 50 ns = 10 mbytes/s. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 73 q&a no.: qah8s-203 category: dmac subject: difference between dmac and dtc question what is the difference between the dmac and the dtc? answer the dmac has data transfer information registers within the module, and performs data transfer on up to four channels. the dmac achieves a high transfer speed of 0.1 s (min.) per channel. the dtc places transfer data information in on-chip ram, and can perform transfer on up to 85 channels. the transfer speed is 0.65 s per channel. the dtc can perform chain transfer in which multiple data transfers are initiated by a single activation source. item dmac dtc notes minimum transfer time 0.1 s 0.65 s at 20 mhz operation transfer information dedicated registers on-chip ram activation sources 13 28 h8s/2655 transfer channels 4 85 chain transfer no yes applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 74 q&a no.: qah8s-204 category: dmac subject: alternate 8-bit/16-bit space accesses question can data transfer be performed between 8-bit space and 16-bit space using the dmac or dtc? answer yes. as the input/output bus width is managed by the bus controller, as long as the bus width is set by the bus controller, the user can use the dmac or dtc without having to be aware of the bus width. f address rd hwr lwr d15 to d8 d7 to d0 16-bit access space (external memory read) 8-bit access space (external memory write) timing of data transfer from 16-bit access space to 8-bit access space
microcomputer technical q&a 75 applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 76 q&a no.: qah8s-205 category: dmac subject: tend signal output conditions when using write buffer function question what are the tend signal output conditions when the write buffer function is used? answer the tend output signal goes low in an external bus cycle if either a dmac read cycle or write cycle is an external access. if a dmac data transfer involves internal addresses, on the other hand, the tend signal is not output while the external bus is used (during external bus release, an external write using the write buffer function, the dram refresh period, etc.). the tend signal is output when the external bus is not in use. dmac tend signal output is shown in the table below. dmac tend signal output dmac access area read write external address ? external address o o internal address ? external address d o external address ? internal address o o internal address ? internal address dd note: d : output when external bus is not being used o : always output
microcomputer technical q&a 77 internal address external address cpu external write cpu external write dmac transfer dmac transfer f low in read/write c y cle tend external read external write example of external address ? external address transfer applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 78 q&a no.: qah8s-206 category: dmac subject: interrupt acceptance after end of transfer question after the transfer count register value reaches h'0000 and an end interrupt is generated while the dmac is being used, when is the next transfer request accepted? answer the next transfer request is accepted when a bit is set to 1 by software in the data transfer control register (dtcr). when the transfer count register value reaches h'0000 and a transfer end interrupt is generated, the dte bit is cleared and data transfer is disabled. to perform transfer again, make the transfer count register setting in the transfer end interrupt routine, then set the dte bit to 1. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 79 q&a no.: qah8s-207 category: dmac subject: handling of transfer request before start of transfer question if a transfer request is generated before the dmac starts transfer, is the request ignored? answer if the activation source is an internal interrupt if the dte bit is 0, a cpu interrupt is requested. when the dte bit is set to 1 while that interrupt is masked by the cpu, an activation request is sent to the dmac. if the activation source is an external request when edge-sensing is selected, the first activation after enabling is performed on detection of a low level, and therefore the request will not be ignored if the low level is held. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 80 q&a no.: qah8s-208 category: dmac subject: activation request signal detection question when the dreq pin is designated falling-edge input, why is the first transfer request performed at the low level? answer if a falling edge at the dreq pin were used for the first activation, it would not be possible to recognize a request at first when transfer is enabled (dte = 1) after the dreq signal falling edge. for this reason, the first activation after transfer is enabled is by low level detection. transfer group a transfer group b invalid recognition dreq normal low level dreq normal high level dreq dte dreq dte dreq and dte timing chart
microcomputer technical q&a 81 applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 82 q&a no.: qah8s-209 category: dmac subject: short address mode and full address mode question what is the difference between the dmacs short address mode and full address mode? answer the dmac requires specification of the source address and destination address in order to perform data transfer. in full address mode, both of these addresses are specified as 24-bit addresses, whereas in short address mode, one is specified as a 24-bit address and the other as a 16-bit address. h'ff is written in the upper 8 bits of the 16-bit address. in short address mode, whether the 16-bit specification is to be used for the source or the destination address can be selected with a register setting. if transfer is to be performed by means of internal interrupts in full address mode, setting a block size of 1 in block transfer mode results in the same operation as for sequential mode in short address mode. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 83 q&a no.: qah8s-210 category: dmac subject: bus right in standby state question in the dmac full address mode and external request mode, a standby state may be entered after a dmac write. what happens to the bus right during this period? answer the dmac releases the bus right in the standby state, and so the bus is transferred to the cpu, refresh controller, etc. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 84 q&a no.: qah8s-211 category: dmac subject: handling of transfer end interrupt questions the manual states that if dte is cleared to 0 when dtie = 1, an interrupt request is sent to the cpu. 1. in the case shown in the figure, will dma transfer end interrupts be generated continually? 2. how can interrupt generation be prevented? dma interrupt handling dte = 0, dtie = 1 dte = 0, dtie = 1 values held rte answers 1. in the case in the figure, interrupts will be generated continually. 2. an interrupt will always be generated if dtie is set to 1 (enabling interrupts) when dte = 0. therefore, either set the dte bit to 1 (the bset instruction can be used) or clear the dtie bit to 0 (the bclr instruction can be used).
microcomputer technical q&a 85 applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 86 q&a no.: qah8s-212 category: dmac subject: dreq signal input question when the dreq pin is used in level-sensing mode, must it be held low until the data transfer ends? answer the dreq signal is latched at the rise of f , and once latched the activation source is held. the activation source will therefore be held if the dreq pin remains low for at least two states. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 h8s/2355 yes h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 87 q&a no.: qah8s-213 category: dtc subject: nature of dtc question is the dtc special hardware, or is the dtc function executed by a cpu microprogram, etc.? answer the dtc consists of special hardware. this enables it to perform high-speed data transfer without imposing any load on the cpu. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 yes h8s/2148 h8s/2144 yes h8s/2138 h8s/2134 yes h8s/2128 h8s/2124
microcomputer technical q&a 88 q&a no.: qah8s-214 category: dtc subject: maximum number of channels question what is the maximum number of dtc channels? answer dtc register information is located in a 1-kbyte area in on-chip ram. the amount of ram required for one dtc transfer is 12 bytes, enabling a maximum of 85 channels to be set. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 yes h8s/2148 h8s/2144 yes h8s/2138 h8s/2134 yes h8s/2128 h8s/2124
microcomputer technical q&a 89 q&a no.: qah8s-215 category: dtc subject: setting register information question are any precautions necessary when setting dtc register information? answer place dtc register information in the 1-kbyte area from h'fff800 to h'fffbff* in on-chip ram, and set the rame bit to 1 in the system control register (syscr). note: * h'ffec00 to h'ffefff in the h8s/2100 series applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 yes h8s/2148 h8s/2144 yes h8s/2138 h8s/2134 yes h8s/2128 h8s/2124
microcomputer technical q&a 90 q&a no.: qah8s-216 category: dtc subject: order of setting register information question is there a particular order for setting dtc register information? answer there is no particular order, but the following point should be noted. if the dtc mode registers (mra/mrb) are set first, followed by the dtc source address register (sar) and dtc destination address register (dar): since sar and dar are 24-bit registers, when sar and dar are set with a longword instruction (mov.l), the previously set mra and mrb information will be corrupted. this can be avoided by making the sar and dar settings by longword access first, followed by the mra and mrb settings. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 yes h8s/2148 h8s/2144 yes h8s/2138 h8s/2134 yes h8s/2128 h8s/2124
microcomputer technical q&a 91 q&a no.: qah8s-217 category: dtc subject: use of dtc interrupt select bit (disel) question how is the disel bit in dtc mode register b (mrb) used? answer the use of the disel bit is shown below. disel description 0 the cpu executes interrupt handling (end processing or activation processing) after completion of the specified number of data transfers. suitable when performing data transfer only. 1 the cpu executes interrupt handling at the end of (end processing or activation processing) at the end of each dtc data transfer. if interrupt handling by the cpu is necessary each time, high-speed execution is possible by having the dtc replace the data transfer section. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 yes h8s/2148 h8s/2144 yes h8s/2138 h8s/2134 yes h8s/2128 h8s/2124
microcomputer technical q&a 92 q&a no.: qah8s-218 category: tpu subject: non-timer use of port question how can the tioc i/o port be used for a purpose other than tpu input/output? answer set b'0000 in bits 7 to 4 or bits 3 to 0 of the timer i/o control register (tior) (disabling output). applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 93 q&a no.: qah8s-219 category: tpu subject: cascaded connection question can cascaded connection be used with the tpu? answer yes. the two timer register combinations shown below can be used. the upper and lower registers operate in synchronization with the clock. 1. tcnt1 + tcnt2 2. tcnt4 + tcnt5 with combination 2, the following points must be noted. longword access cannot be used on the tcnt4/tcnt5 (tcnt, tgr) register pair, so two word accesses must be used. consequently, there will be a lag between the read/write timings of the upper and lower registers. compare matches occur separately for the upper and lower registers. in the case of an upper register compare match, in particular, care is required if the lower counter overflows or underflows. note: tctn4 and tcnt5 are not provided in the h8s/2245 series. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 94 q&a no.: qah8s-220 category: tpu subject: dual use of pwm mode 1 and input capture question when tpu channels 0 and 3 are set to pwm mode 1 and only timer general registers tgrna and tgrnb are used, can the remaining timer general registers (tgrnc and tgrnd) be used for input capture? answer no. there is one operating mode per channel. tgrnc and tgrnd can be used as output compare registers by disabling output. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 95 q&a no.: qah8s-221 category: tpu subject: setting pwm mode 2 cycle question which register is used to set the cycle in pwm mode 2? answer the cycle is determined by the register selected by cclrn (counter clear) in the timer control register (tcr). in this case, output is automatically disabled for the output pins corresponding to the register used as the counter clear source. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 96 q&a no.: qah8s-222 category: tpu subject: synchronous operation of two sets question is synchronous operation of two sets possible? answer no. the timer synchro register (tsyr) does not permit a synchronous operation setting for two or more sets. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 97 q&a no.: qah8s-223 category: tpu subject: two-phase pwm output question is it possible to obtain two-phase pwm output with a common cycle but different duty cycles and a phase difference? answer this is possible in pwm mode 1, using channels 0 and 3 (or synchronous operation of two channels). the setting method for channel 0 is described below. 1. set channel 0 to pwm mode. 2. set tgra and tgrb, and tgrc and tgrd, to different output with the timer i/o control register (tior). 3. set a common cycle in tgrd, and set counter clearing by a tgrd compare match. 4. set the phase difference in tgra. also, set the tioc output duty cycle in tgrc so that tgrb C tgra is the tioca output duty cycle. tcnt value tgr0d tgr0b tgr0c tgr0a h'0000 tioca0 tiocc0 time two-phase pwm output
microcomputer technical q&a 98 applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 99 q&a no.: qah8s-224 category: wdt subject: interval timer with arbitrary time interval question when the wdt is used as an interval timer, is it possible generate interrupts at fixed intervals? answer yes. however, since the wdt generates only overflow interrupts*, the initial value should be written in tcnt. note that tcnt is always in the reset state when tme = 0. note: * an nmi interrupt setting can also be made in the h8s/2100 series. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 100 q&a no.: qah8s-225 category: sci subject: sci initialization question in sci initialization, why is there a minimum 1-bit wait before the te bit or re bit is set in the serial control register (scr)? answer this 1-bit interval is the minimum time necessary for internal processing to fix the data. if transmission is performed without this 1-bit wait, indefinite data will be transmitted. a wait of at least 1-bit duration is therefore essential before performing transmission. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 101 q&a no.: qah8s-226 category: sci subject: difference between tdre flag and tend flag question what is the difference between the tdre flag and tend flag in the serial status register (ssr)? answer the tdre flag indicates that the transmit data register (tdr) is in the write-enabled state, without regard to the internal state of the transmit shift register (tsr). the tend flag indicates that tsr is empty, and tdr is in the write-enabled state. the status of the tend flag should be checked to confirm whether all data has been transmitted. tdr tdr tsr tsr tdre generation state tend generation state (empty) (empty) (empty) data tdre and tend generation states applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 102 q&a no.: qah8s-227 category: sci subject: initial state of txd pin question what happens to the initial value of the txd pin when the te bit is set to 1 in the serial control register (scr) in serial transmission? answer when the te bit is set to 1, the txd pin goes high automatically in both asynchronous mode and synchronous mode. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 103 q&a no.: qah8s-228 category: sci subject: maximum external clock input value (asynchronous mode) question what is the maximum possible external clock input frequency in asynchronous mode? answer the cycle of the external clock input to the sci must be at least 4 t cyc (min.). with a 20 mhz operating frequency, the maximum value for external clock input is 5 mhz (max.). applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 104 q&a no.: qah8s-229 category: sci subject: transmit/receive operation in synchronous mode question can reception alone be performed in transmit/receive operation (te = re = 1) in synchronous mode? answer as the same clock is used for transmission and reception in synchronous mode, transmission and reception are performed simultaneously in transmit/receive operation (te = re = 1). consequently, transmit/receive operation cannot be performed until transmission is started (tdre is cleared to 0). when the h8s series chip performs clock output, when tdre is cleared to 0 the clock is output and transmission and reception are performed simultaneously. when the h8s series chip uses clock input, tdre should be cleared to 0 before inputting the clock. the clock will be ignored if input before tdre is cleared to 0. to perform reception only, write dummy data to tdr to clear tdre to 0. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 105 q&a no.: qah8s-230 category: sci subject: sci transmission using dtc question is it possible to performs sci transmission by activating the dtc at successive timer compare matches? answer no. the reason is that, in dtc data transfer, tdre is cleared to 0 in the serial data register (ssr) only when the dtc activation source is the sci transmission-completed interrupt. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 106 q&a no.: qah8s-231 category: sci subject: permissible bit rate error in asynchronous mode question what is the permissible bit rate error in asynchronous mode? answer when the h8s series chip is receiving, the permissible error within one frame is as shown below. this shows the worst case for the sampling timing of the last bit (stop bit) of the frame. with 8-bit data and no parity, one frame consists of 160 internal basic clocks. assuming no per-bit distortion, the conditions under which the stop bit can be sampled are as follows: when transmitting side is slow: 7.5/160 = 0.046 when transmitting side is fast: C7/160 = C0.043 from the above two points, the permissible error can be calculated to be approximately 4.3% this is a theoretical value. a margin should be allowed on the system side in actual system designs.
microcomputer technical q&a 107 01234 0 123 4 567p 5 5 6 7 8 150 1 5 6 7 8 14150 13 16 clocks 160 clocks start stop start typ. a b clk rxd (typ) rxd (typ) rxd (min) rxd (a) sync data sample start bit start bit start bit start bit sampling drift: 1 clock max. stop stop bit stop bit sampling possible even with 7.5-clock drift with bit drift sampling drift: 1 clock max. 1 clock stop bit error will result if stop bit cannot be sampled here = +7.5/160 = ?/160 with bit drift enlarged diagram sampling possible even with 7-clock drift receive margins in asynchronous mode
microcomputer technical q&a 108 however, if the transmitting side is fast, the next frame will begin before completion of the receive operation, and it may not be possible to receive this next frame. two-stop mode should therefore be used when receiving, since the second stop bit is ignored in this mode. note: see receive data sampling timing in asynchronous mode and receive margin in the hardware manual. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 109 q&a no.: qah8s-232 category: sci subject: operation of rdrf flag question an operation to clear the rdrf flag to 0 in the serial status register (ssr) is necessary in sci reception. what will happen if this flag is cleared to 0 directly without first reading 1? answer it will not be cleared. however, if the bclr instruction is used, after a byte-unit read of ssr, the rdrf flag is cleared to 0, and a byte-unit write is performed. therefore, the rdrf flag can be cleared to 0 with a bclr instruction when the flag is set to 1 (in the rxi interrupt handling routine). applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 110 q&a no.: qah8s-233 category: sci subject: rdrf flag set timing questions when data reception ends, the rdrf flag is set to 1 in the serial status register (ssr). 1. what is the timing for rdrf flag setting in asynchronous mode? 2. what is the timing for rdrf flag setting in synchronous mode? answers see the next page. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 111 answers 1. the rdrf flag is set following the fall of the data sampling clock after the stop bit data is received (see figure below). 1234 5678910111213141516 1234 5678910111213141516 bit 7 stop bit base clock receive data data sampling rdrf when sck clock source is internal clock: 0.5 base clock + 2 states when sck clock source is external clock: 3 to 4 states with 8-bit data and 1 stop bit
microcomputer technical q&a 112 2. the rdrf flag is set following the fall of the serial clock after the msb data is received (see figure below). bit 6 bit 7 serial clock receive data rdrf when sck clock source is internal clock: 1 state when sck clock source is external clock: 2 to 3 states in synchronous mode
microcomputer technical q&a 113 q&a no.: qah8s-234 category: sci subject: interrupt source flag clearing question if a receive-error interrupt is generated, and the receive error flags (orer, fer, per) in the serial status register (ssr) are not cleared in the interrupt handling routine before returning to the main routine, will another receive-error interrupt be generated? answer yes. as the receive error flags are not cleared to 0 automatically, another receive-error interrupt will be generated on return to the main routine (on execution of the rte instruction). note: the interrupt will be generated as soon as interrupt masking is released. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 114 q&a no.: qah8s-235 category: sci subject: continuous transmission/reception in synchronous mode using external clock questions in synchronous mode operation using an external clock: 1. if, after transmission of one data byte is completed, the external clock is input to the sck pin before the cpu has written the next transmit data to the transmit data register (tdr), will the sci start the next transmit operation? 2. what happens after completion of reception? 3. what will happen if the tdre bit is cleared to 0 in the serial status register (ssr) without writing transmit data to tdr? answers 1. no, transmission will not be started. the next transmission is not performed until the tdre bit is cleared to 0 in the serial status register (ssr). 2. reception is started. however, if the rdrf bit is not cleared to 0 in ssr before reception of the next data is completed, an overrun error will occur. 3. the first time, h'ff (the initial value of tdr) will be transmitted. from the second time onward, the previous tdr value will be transmitted. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 115 q&a no.: qah8s-236 category: sci subject: use of rdr and tdr when sci is not used questions can the following registers be used as data registers when the sci is not used? 1. receive data register (rdr) 2. transmit data register (tdr) answers 1. no: as the receive data register (rdr) is a read-only register, it cannot be used as a data register. 2. yes, the transmit data register (tdr) can be used as a data register. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 116 q&a no.: qah8s-237 category: sci subject: sci clock pin input/output setting question when the sci is used, is the input/output specification for the sck pin made in the data direction register (ddr) for the port corresponding to that pin? answer no. when the sci is used, the sck pin input/output specification is made with the c/ a bit (communication mode bit) in the serial mode register (smr) and bits cke1 and cke0 (clock enable) in the serial control register (scr). a setting is not required in the ddr for the corresponding port. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 117 q&a no.: qah8s-238 category: sci subject: serial internal i/o pin states question after the txd, rxd, and sck pinswhich are multiplexed as i/o portswere used as sci pins, sci operation was disabled with the serial control register (scr) and serial mode register (smr), and these pins were set as i/o ports. in this case, what is the data direction register (ddr) value for each of these pins? answer sci operation does not affect the contents of i/o port data direction registers. therefore, when the pins are used as described above, ddr will retain the values it held before the pins were set as sci pins. the data register (dr) values are similarly retained. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 118 q&a no.: qah8s-239 category: sci subject: setting asynchronous mode question when performing asynchronous mode transfer with the sci, what is the setting procedure for performing transfer by software, without using the dmac or dtc? answer when tdre = 1, a data-empty interrupt is always generated when tie is set to 1. there are thus two methods, as follows. 1. performing first byte setting in the txi interrupt handling routine sci setting processing interrupt wait counter setting: count = 0 te = 1 tie = 1
microcomputer technical q&a 119 2. performing first byte setting at the same time as sci setting sci setting processing interrupt wait counter setting: count = 1 te = 1 clear tdre (start transfer) * tie = 1 (enable empty interrupt) as 1st data byte is stored in tdr by software, counter is set to 1. set 1st byte in tdr note: * after the data is transferred from tdr to tsr, tdre is set to 1.
microcomputer technical q&a 120 in both of the above cases, the txi interrupt handling routine flowchart is as shown below. txi interrupt count++ count = 16 write (count)'th data byte to tdr clear tdre (tdre read-clear) rte tie = 0 (disable interrupts) no yes applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 121 q&a no.: qah8s-240 category: sci subject: data transfer to tdr questions sram h8s series chip data transmission sci dmac or dtc 16-bit data bus transfer data to transfer data in 16-bit-access space* to the sci transmit data register (tdr: 8 bits long), as shown above: 1. is there any way of performing the transfer by software? 2. is there any way of performing the transfer with the dmac? note: * the h8s/2138, h8s/2134, h8s/2128, and h8s/2124 series have only 8-bit-access space. answers 1. transfer by software byte access can also be used in 16-bit-access space. read the transfer data in sram one byte at a time, and transfer it to the scis tdr (using the mov.b instruction). 2. transfer using dmac or dtc designate the txi interrupt as the dmac or dtc activation source, set the data size as byte, and transfer the transfer data in sram to the scis tdr one byte at a time. (word-size transfer is not possible, since the dmac or dtc is activated each time one byte is transmitted.)
microcomputer technical q&a 122 applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 123 q&a no.: qah8s-241 category: sci subject: tdre flag set timing questions when data transmission ends, the tdre flag is set to 1 in the serial status register (ssr). 1. what is the timing for tdre flag setting in asynchronous mode? 2. what is the timing for tdre flag setting in synchronous mode? answers see the next page. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 124 answers the tdre set timing differs depending on whether or not the transmit shift register (tsr) contains transmit data. 1. asynchronous mode a. when tsr contains transmit data (see figure below) 1234 5678910111213141516 1234 5678910111213141516 stop bit start bit base clock transmit data tdre when sck clock source is internal clock: 4 states when sck clock source is external clock: 4 to 5 states this timing also applies when transmission is started by setting the te (transmit enable) bit.
microcomputer technical q&a 125 b. when tsr does not contain transmit data (see figure below) 9 9 10111213141516 1 2 3 4 5 6 7 8 10111213141516 1 2 3 4 5 6 7 8 base clock f internal write signal tdre 2.5 states t1 t2 t3
microcomputer technical q&a 126 2. synchronous mode a. when tsr contains transmit data (see figure below) when sck clock source is internal clock: 2 states when sck clock source is external clock: 1.5 to 2.5 states bit 6 bit 7 serial clock transmit data tdre b. when tsr does not contain transmit data (see figure below) f internal write signal tdre 2.5 states t1 t2 t3
microcomputer technical q&a 127 q&a no.: qah8s-242 category: sci subject: phases of system clock and sck question is sck (the serial clock transfer clock) output in synchronization with the rise or fall of f (the system clock)? answer the sck signal is output in synchronization with the fall of f . applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 128 q&a no.: qah8s-243 category: a/d converter subject: idea behind external c and r question what is the idea behind the connection of a signal source impedance (tap resistance, etc.) and low- pass filter to the a/d converter input pins? answer the ideas behind these connections are as follows. permissible signal source impedance the analog inputs of h8s series chips are designed so that conversion accuracy is guaranteed for an input signal with a permissible signal source impedance, r out , of 5 k w or less (when f > 12 mhz). the figure below shows an equivalent circuit of the analog input circuit. in order for a/d converter to be performed correctly, internal capacitance c ad must be charged within the sampling period, t spl . charge time constant t is expressed as t = c ad (r out + r ad ), so that, for a permissible conversion error of 4 lsb, for example, the calculation is as follows: v cc 1020/1024 > v cc (1-exp (Ct spl / t )) \ t spl > 5.6 t = 5.6 c ad (r out + r ad ) if t spl = 2 s ( f = 16 mhz, cks = 1), c ad = 20 pf and r ad = 10 k w ; thus: t < 360 ns \ r out < 8 k w
microcomputer technical q&a 129 a/d converter equivalent circuit c ad ? 20 pf r ad ? 10 k w r out low-pass filter c permissible signal source impedance sensor input an0 to an7 example of analog input circuit low-pass filter adding a large capacitance (up to 0.1 f or so) to the input pins makes sensor output impedance r out essentially negligible in single-mode conversion. when scan mode is used, however, the internal capacitance must be charged in a short time, and so error may arise. therefore, if permissible signal source impedance r out exceeds 5 k w and a low-pass filter is added, use of single mode is recommended, with the following times set for conversion cycle t int . t int > 2 ms (100 k w 3 r out > 5 k w ) t int > 4 ms (200 k w 3 r out > 100 k w ) applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 130 q&a no.: qah8s-244 category: a/d converter subject: a/d conversion in simultaneous sampling operation question how does a/d conversion operate with group scan mode simultaneous sampling? answer an example of a/d conversion operation with group scan mode simultaneous sampling is shown below. adst addra addrb addrc addrd idle idle sample a conver- sion a idle sample c sample c conver- sion c idle sample a conver- sion a idle conversion b sample b idle conversion d sample d sample d idle conversion b sample b idle result a result b result c result d result a result b example of group scan mode simultaneous sampling operation
microcomputer technical q&a 131 applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 132 q&a no.: qah8s-245 category: a/d converter subject: a/d conversion time in simultaneous sampling operation question what is the a/d conversion time in simultaneous sampling operation? answer the conversion time is normally 1 s, but with simultaneous sampling, as shown in the figure below, the conversion time for even-numbered conversions (b and d) is twice that for odd- numbered conversions (a and c). the conversion time is thus 1 s for even-numbered conversions and 2 s for odd-numbered conversions. sample a sample b sample c sample d t d 0.15 m s (3 cycles) t spl 1 m s (20 cycles) t cp 1 m s (20 cycles) t cp 2 m s (40 cycles) t spl 1 m s (20 cycles) t cp 1 m s (20 cycles) t cp 2 m s (40 cycles) t f 0.05 m s (1 cycle) f address write signal adst sampling timing a/d conversion operation timing adf conversion a conversion b conversion c conversion d (20 mhz) a/d conversion times in simultaneous sampling operation
microcomputer technical q&a 133 applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 134 q&a no.: qah8s-246 category: i/o ports subject: i/o port manipulation question when a particular bit of an i/o port is specified as an output port, can a bit-manipulation instruction be executed on that port? answer yes. the port data registers (drs) can be read or written to at any time, and can be manipulated with bit-manipulation instructions. the data direction registers (ddrs) are write-only registers, and so cannot be manipulated with bit-manipulation instructions. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 135 q&a no.: qah8s-247 category: i/o ports subject: reserved bits question write data rules are sometimes given for reserved bits in internal i/o registers. is there any problem with writing data other than that prescribed to these reserved bits? answer only the data prescribed in the manual should be written, otherwise correct operation is not guaranteed. for example, the ice and the production chip may operate differently. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 136 q&a no.: qah8s-248 category: i/o ports subject: disabling f output question is there any way of fixing f output high in normal operation? answer yes. to fix f output high, set the pstop bit to 1 in the system clock control register (sckcr) (see table below). also, f output can be disabled by clearing the corresponding port data direction register (ddr) bit to 0, designating input port operation. disabling or fixing f output is effective in reducing peripheral noise, current dissipation, etc. f pin states in each processing state ddr 0 1 pstop 0 1 hardware standby mode high impedance high impedance high impedance software standby mode high impedance fixed high fixed high sleep mode high impedance f output fixed high normal operating state high impedance f output fixed high applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 137 q&a no.: qah8s-249 category: i/o ports subject: port 3 open-drain output question port 3 pins are multiplexed as sci0 and sci1 input/output pins. can port 3 pins be used as open- drain outputs only when the i/o port function is used, or also when the sci output pin function is used? answer open-drain output is also possible when port 3 pins are used as sci output pins. in both i/o port operation and sci output pin operation, open-drain output can be selected by setting port 3 open-drain control register (p3odr) bits to 1. after making the p3odr setting, set the relevant pins to output mode. note: when open-drain output is used, it is still necessary to ensure that the relevant pin levels do not exceed the input voltage range values specified in the electrical characteristics section. applicable products applicability series applicability series applicability series entire h8s series yes h8s/2655 yes h8s/2350 yes h8s/2355 yes h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 138 q&a no.: qah8s-250 category: i/o ports subject: multiplexing as irq3 and lwr question the pf3 pin is also multiplexed as lwr and irq3 . can irq3 input be used in modes 1, 2, 4, 5, and 6? answer no. the pf3/ lwr / irq3 pin becomes the lwr output automatically in modes 1, 2, 4, 5, and 6, and so cannot be used as the irq3 input. applicable products applicability series applicability series applicability series entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 yes h8s/2345 yes h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124
microcomputer technical q&a 139 q&a no.: qah8s-251 category: clock pulse generator subject: crystal resonator capacitance value question crystal resonator capacitance value c0 is given as 7 pf in the hardware manual. can a larger capacitance be used? answer the c0 value given in the hardware manual is a reference value. the c0 value will depend on the users system, and therefore oscillation should be confirmed in with the chip in actual use. applicable products applicability series applicability series applicability series yes entire h8s series h8s/2655 h8s/2350 h8s/2355 h8s/2357 h8s/2345 h8s/2245 h8s/2148 h8s/2144 h8s/2138 h8s/2134 h8s/2128 h8s/2124

h8s series technical q&a application note publication date: 1st edition, february 1998 published by: semiconductor and ic div. hitachi, ltd. edited by: technical documentation center hitachi microcomputer system ltd. co py ri g ht ? hitachi, ltd., 1998. all ri g hts reserved. printed in ja p an.

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